KoDer/espLinuxESPIDF
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

hz

Browse Source
This commit is contained in:
KoDer
2026-05-06 19:51:30 +07:00
commit 3958b0edcf
2704 changed files with 410390 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/board.cmake
Executable
+16
View File
@@ -0,0 +1,16 @@
set(CMAKE_SYSTEM_CPU cortex-m85 CACHE INTERNAL "System Processor")
set(MCU_VARIANT ra8m1)
set(JLINK_DEVICE R7FA8M1AH)
#set(JLINK_OPTION "-USB 001083115236")
# device default to PORT 1 High Speed
if (NOT DEFINED RHPORT_DEVICE)
set(RHPORT_DEVICE 1)
endif()
if (NOT DEFINED RHPORT_HOST)
set(RHPORT_HOST 0)
endif()
function(update_board TARGET)
endfunction()
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/board.h
Executable
+47
View File
@@ -0,0 +1,47 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2023 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: RA8M1 EK
url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
#define LED_STATE_ON 1
#define BUTTON_STATE_ACTIVE 0
#ifdef __cplusplus
}
#endif
#endif
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/board.mk
Executable
+11
View File
@@ -0,0 +1,11 @@
CPU_CORE = cortex-m85
MCU_VARIANT = ra8m1
# For flash-jlink target
JLINK_DEVICE = R7FA8M1AH
# Port 1 is highspeed
RHPORT_DEVICE ?= 1
RHPORT_HOST ?= 0
flash: flash-jlink
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex
Executable
BIN
View File
Binary file not shown.
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug
Executable
+231
View File
@@ -0,0 +1,231 @@
/*********************************************************************
*
* OnProjectLoad
*
* Function description
* Project load routine. Required.
*
**********************************************************************
*/
void OnProjectLoad (void) {
Project.SetTraceSource ("Trace Pins");
Project.SetDevice ("R7FA8M1AH");
Project.SetHostIF ("USB", "");
Project.SetTargetIF ("SWD");
Project.SetTIFSpeed ("50 MHz");
Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M85F.svd");
Project.AddSvdFile ("../../../../../../../cmsis-svd-data/data/Renesas/R7FA6M5BH.svd");
File.Open ("../../../../../../examples/cmake-build-ra8m1_ek/device/cdc_msc/cdc_msc.elf");
}
/*********************************************************************
*
* BeforeTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
void BeforeTargetConnect (void) {
// Trace pin init is done by J-Link script file as J-Link script files are IDE independent
//Project.SetJLinkScript("../../../debug.jlinkscript");
Project.SetJLinkScript ("$(ProjectDir)/Renesas_RA8_TracePins.pex");
}
/*********************************************************************
*
* AfterTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetConnect (void) {
//}
/*********************************************************************
*
* TargetDownload
*
* Function description
* Replaces the default program download routine. Optional.
*
**********************************************************************
*/
//void TargetDownload (void) {
//}
/*********************************************************************
*
* BeforeTargetDownload
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDownload (void) {
//}
/*********************************************************************
*
* AfterTargetDownload
*
* Function description
* Event handler routine. Optional.
* The default implementation initializes SP and PC to reset values.
*
**********************************************************************
*/
void AfterTargetDownload (void) {
_SetupTarget();
}
/*********************************************************************
*
* BeforeTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetHalt
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetHalt (void) {
//}
/*********************************************************************
*
* BeforeTargetResume
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetResume (void) {
//}
/*********************************************************************
*
* OnSnapshotLoad
*
* Function description
* Called upon loading a snapshot. Optional.
*
* Additional information
* This function is used to restore the target state in cases
* where values cannot simply be written to the target.
* Typical use: GPIO clock needs to be enabled, before
* GPIO is configured.
*
**********************************************************************
*/
//void OnSnapshotLoad (void) {
//}
/*********************************************************************
*
* OnSnapshotSave
*
* Function description
* Called upon saving a snapshot. Optional.
*
* Additional information
* This function is usually used to save values of the target
* state which can either not be trivially read,
* or need to be restored in a specific way or order.
* Typically use: Memory Mapped Registers,
* such as PLL and GPIO configuration.
*
**********************************************************************
*/
//void OnSnapshotSave (void) {
//}
/*********************************************************************
*
* OnError
*
* Function description
* Called when an error occurred. Optional.
*
**********************************************************************
*/
//void OnError (void) {
//}
/*********************************************************************
*
* AfterProjectLoad
*
* Function description
* After Project load routine. Optional.
*
**********************************************************************
*/
//void AfterProjectLoad (void) {
//}
/*********************************************************************
*
* _SetupTarget
*
* Function description
* Setup the target.
* Called by AfterTargetReset() and AfterTargetDownload().
*
* Auto-generated function. May be overridden by Ozone.
*
**********************************************************************
*/
void _SetupTarget(void) {
unsigned int SP;
unsigned int PC;
unsigned int VectorTableAddr;
VectorTableAddr = Elf.GetBaseAddr();
//
// Set up initial stack pointer
//
SP = Target.ReadU32(VectorTableAddr);
if (SP != 0xFFFFFFFF) {
Target.SetReg("SP", SP);
}
//
// Set up entry point PC
//
PC = Elf.GetEntryPointPC();
if (PC != 0xFFFFFFFF) {
Target.SetReg("PC", PC);
} else {
Util.Error("Project script error: failed to set up entry point PC", 1);
}
}
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
Executable
+62
View File
@@ -0,0 +1,62 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define RA_NOT_DEFINED 0
#ifndef BSP_CFG_RTOS
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (2)
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (1)
#else
#define BSP_CFG_RTOS (0)
#endif
#endif
#ifndef BSP_CFG_RTC_USED
#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
#endif
#undef RA_NOT_DEFINED
#if defined(_RA_BOOT_IMAGE)
#define BSP_CFG_BOOT_IMAGE (1)
#endif
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
#define BSP_CFG_HEAP_BYTES (0x1000)
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
#define BSP_CFG_ASSERT (0)
#define BSP_CFG_ERROR_LOG (0)
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_EARLY_INIT ((0))
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#ifdef __cplusplus
}
#endif
#endif /* BSP_CFG_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
Executable
+5
View File
@@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_CFG_H_
#define BSP_MCU_DEVICE_CFG_H_
#define BSP_CFG_MCU_PART_SERIES (8)
#endif /* BSP_MCU_DEVICE_CFG_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
Executable
+11
View File
@@ -0,0 +1,11 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA8M1AHECBD
#define BSP_MCU_FEATURE_SET ('A')
#define BSP_ROM_SIZE_BYTES (2064384)
#define BSP_RAM_SIZE_BYTES (917504)
#define BSP_DATA_FLASH_SIZE_BYTES (12288)
#define BSP_PACKAGE_BGA
#define BSP_PACKAGE_PINS (224)
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
Executable
+526
View File
@@ -0,0 +1,526 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h"
#include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h"
#include "bsp_clock_cfg.h"
#define BSP_MCU_GROUP_RA8M1 (1)
#define BSP_LOCO_HZ (32768)
#define BSP_MOCO_HZ (8000000)
#define BSP_SUB_CLOCK_HZ (0)
#if BSP_CFG_HOCO_FREQUENCY == 0
#define BSP_HOCO_HZ (16000000)
#elif BSP_CFG_HOCO_FREQUENCY == 1
#define BSP_HOCO_HZ (18000000)
#elif BSP_CFG_HOCO_FREQUENCY == 2
#define BSP_HOCO_HZ (20000000)
#elif BSP_CFG_HOCO_FREQUENCY == 4
#define BSP_HOCO_HZ (32000000)
#elif BSP_CFG_HOCO_FREQUENCY == 7
#define BSP_HOCO_HZ (48000000)
#else
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
#endif
#define BSP_CFG_FLL_ENABLE (0)
#define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1)
#define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1)
#define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1)
#define BSP_CFG_RTOS_IDLE_SLEEP (0)
#define BSP_CFG_CLOCK_SETTLING_DELAY_US (150)
#if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100)
#define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U)
#elif defined(BSP_PACKAGE_LQFP)
#define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U)
#else
#define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U)
#endif
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
#define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
#if defined(_RA_TZ_SECURE)
#define BSP_TZ_SECURE_BUILD (1)
#define BSP_TZ_NONSECURE_BUILD (0)
#elif defined(_RA_TZ_NONSECURE)
#define BSP_TZ_SECURE_BUILD (0)
#define BSP_TZ_NONSECURE_BUILD (1)
#else
#define BSP_TZ_SECURE_BUILD (0)
#define BSP_TZ_NONSECURE_BUILD (0)
#endif
/* TrustZone Settings */
#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
/* CMSIS TrustZone Settings */
#define SCB_CSR_AIRCR_INIT (1)
#define SCB_AIRCR_BFHFNMINS_VAL (0)
#define SCB_AIRCR_SYSRESETREQS_VAL (1)
#define SCB_AIRCR_PRIS_VAL (0)
#define TZ_FPU_NS_USAGE (1)
#ifndef SCB_NSACR_CP10_11_VAL
#define SCB_NSACR_CP10_11_VAL (3U)
#endif
#ifndef FPU_FPCCR_TS_VAL
#define FPU_FPCCR_TS_VAL (1U)
#endif
#define FPU_FPCCR_CLRONRETS_VAL (1)
#ifndef FPU_FPCCR_CLRONRET_VAL
#define FPU_FPCCR_CLRONRET_VAL (1)
#endif
/* Type 1 Peripheral Security Attribution */
/* Peripheral Security Attribution Register (PSAR) Settings */
#ifndef BSP_TZ_CFG_PSARB
#define BSP_TZ_CFG_PSARB (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \
(1 << 15) /* ETHERC/EDMAC */ | \
(1 << 16) /* OSPI */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */)
#endif
#ifndef BSP_TZ_CFG_PSARC
#define BSP_TZ_CFG_PSARC (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E51A */)
#endif
#ifndef BSP_TZ_CFG_PSARD
#define BSP_TZ_CFG_PSARD (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */)
#endif
#ifndef BSP_TZ_CFG_PSARE
#define BSP_TZ_CFG_PSARE (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */)
#endif
#ifndef BSP_TZ_CFG_MSSAR
#define BSP_TZ_CFG_MSSAR (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */)
#endif
/* Type 2 Peripheral Security Attribution */
/* Security attribution for RSTSRn registers. */
#ifndef BSP_TZ_CFG_RSTSAR
#define BSP_TZ_CFG_RSTSAR (0x00000007U)
#endif
/* Security attribution for registers of LVD channels. */
#ifndef BSP_TZ_CFG_LVDSAR
/* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */
#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0)
#define BSP_TZ_CFG_LVDSAR (0U)
#else
#define BSP_TZ_CFG_LVDSAR (3U)
#endif
#endif
/* Security attribution for LPM registers.
* - OPCCR based on clock security.
* - Set remaining registers based on LPM security.
*/
#ifndef BSP_TZ_CFG_LPMSAR
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\
0x002E0106U | \
(BSP_CFG_CLOCKS_SECURE == 0)))
#endif
/* Deep Standby Interrupt Factor Security Attribution Register. */
#ifndef BSP_TZ_CFG_DPFSAR
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xAF1FFFFFU)
#endif
/* RAM Standby Control Security Attribution Register. */
#ifndef BSP_TZ_CFG_RSCSAR
#define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU)
#endif
/* Security attribution for CGC registers. */
#ifndef BSP_TZ_CFG_CGFSAR
#if BSP_CFG_CLOCKS_SECURE
/* Protect all CGC registers from Non-secure write access. */
#define BSP_TZ_CFG_CGFSAR (0U)
#else
/* Allow Secure and Non-secure write access. */
#define BSP_TZ_CFG_CGFSAR (0x047F3BFDU)
#endif
#endif
/* Security attribution for Battery Backup registers. */
#ifndef BSP_TZ_CFG_BBFSAR
#if 0
#define BSP_TZ_CFG_BBFSAR (0U)
#else
#define BSP_TZ_CFG_BBFSAR (0x1FU)
#endif
#endif
/* Security attribution for Battery Backup registers (VBTBKRn). */
#ifndef BSP_TZ_CFG_VBRSABAR
#if 0
#define BSP_TZ_CFG_VBRSABAR (0xFFE0)
#else
#define BSP_TZ_CFG_VBRSABAR (0xED00)
#endif
#endif
/* Security attribution for registers for IRQ channels. */
#ifndef BSP_TZ_CFG_ICUSARA
#define BSP_TZ_CFG_ICUSARA (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */)
#endif
/* Security attribution for NMI registers. */
#ifndef BSP_TZ_CFG_ICUSARB
#define BSP_TZ_CFG_ICUSARB (0 | 0U) /* Should match AIRCR.BFHFNMINS. */
#endif
/* Security attribution for registers for DMAC channels */
#ifndef BSP_TZ_CFG_DMACCHSAR
#define BSP_TZ_CFG_DMACCHSAR (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */)
#endif
/* Security attribution registers for WUPEN0. */
#ifndef BSP_TZ_CFG_ICUSARE
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U)
#endif
/* Security attribution registers for WUPEN1. */
#ifndef BSP_TZ_CFG_ICUSARF
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x00007F08U)
#endif
/* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */
#ifndef BSP_TZ_CFG_TEVTRCR
#define BSP_TZ_CFG_TEVTRCR (0)
#endif
/* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */
#ifndef BSP_TZ_CFG_ELCSARA
#define BSP_TZ_CFG_ELCSARA (0x00000007U)
#endif
/* Set DTCSTSAR if the Secure program uses the DTC. */
#if RA_NOT_DEFINED == RA_NOT_DEFINED
#define BSP_TZ_CFG_DTC_USED (0U)
#else
#define BSP_TZ_CFG_DTC_USED (1U)
#endif
/* Security attribution of FLWT and FCKMHZ registers. */
#ifndef BSP_TZ_CFG_FSAR
/* If the CGC registers are only accessible in Secure mode, than there is no
* reason for nonsecure applications to access FLWT and FCKMHZ. */
#define BSP_TZ_CFG_FSAR (\
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\
((RA_NOT_DEFINED) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \
((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\
((RA_NOT_DEFINED) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */)
#endif
/* Security attribution for SRAM registers. */
#ifndef BSP_TZ_CFG_SRAMSAR
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
#define BSP_TZ_CFG_SRAMSAR (\
((1U) << 0U) | /* SRAMSA0 */\
((1U) << 1U) | /* SRAMSA1 */\
((1U) << 7U) | /* STBRAMSA */\
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */)
#endif
/* Security attribution for the DMAC Bus Master MPU settings. */
#ifndef BSP_TZ_CFG_MMPUSARA
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR)
#endif
/* Security Attribution Register A for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARA
#define BSP_TZ_CFG_BUSSARA (1U)
#endif
/* Security Attribution Register B for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARB
#define BSP_TZ_CFG_BUSSARB (1U)
#endif
/* Security Attribution Register C for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARC
#define BSP_TZ_CFG_BUSSARC (1U)
#endif
/* Enable Uninitialized Non-Secure Application Fallback. */
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
#endif
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
#define OFS_SEQ5 (1 << 28) | (1 << 30)
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
#define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU)
/* Option Function Select Register 1 Security Attribution */
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
#define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U)))
#else
#define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U)
#endif
#endif
#define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25)
#define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) | (1 << 8) | (1 << 24) | (BSP_CFG_ROM_REG_OFS1_INITECCEN))
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
/* Dual Mode Select Register */
#ifndef BSP_CFG_ROM_REG_DUALSEL
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
#endif
/* Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_BPS0
#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
#endif
/* Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_BPS1
#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
#endif
/* Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_BPS2
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
#endif
/* Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_BPS3
#define BSP_CFG_ROM_REG_BPS3 (~( 0U))
#endif
/* Permanent Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_PBPS0
#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
#endif
/* Permanent Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_PBPS1
#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
#endif
/* Permanent Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_PBPS2
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
#endif
/* Permanent Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_PBPS3
#define BSP_CFG_ROM_REG_PBPS3 (~( 0U))
#endif
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
#endif
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
#endif
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
#endif
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
#endif
/* Security Attribution for Bank Select Register */
#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
#define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
/* FSBL Control Register 0 */
#ifndef BSP_CFG_ROM_REG_FSBLCTRL0
#define BSP_CFG_ROM_REG_FSBLCTRL0 ( \
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \
(7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | \
0xFFFFF000)
#endif
/* FSBL Control Register 1 */
#ifndef BSP_CFG_ROM_REG_FSBLCTRL1
#define BSP_CFG_ROM_REG_FSBLCTRL1 ( \
(3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | \
0xFFFFFFFC)
#endif
/* FSBL Control Register 2 */
#ifndef BSP_CFG_ROM_REG_FSBLCTRL2
#define BSP_CFG_ROM_REG_FSBLCTRL2 ( \
(15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \
(0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | \
0xFFFFFE00)
#endif
/* Start Address of Code Certificate Register 0 */
#ifndef BSP_CFG_ROM_REG_SACC0
#define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF)
#endif
/* Start Address of Code Certificate Register 1 */
#ifndef BSP_CFG_ROM_REG_SACC1
#define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF)
#endif
/* Start Address of Measurement Report Register */
#ifndef BSP_CFG_ROM_REG_SAMR
#define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF)
#endif
#ifndef BSP_CFG_DCACHE_ENABLED
#define BSP_CFG_DCACHE_ENABLED (0)
#endif
#ifndef BSP_CFG_SDRAM_ENABLED
#define BSP_CFG_SDRAM_ENABLED (0)
#endif
#ifndef BSP_CFG_SDRAM_TRAS
#define BSP_CFG_SDRAM_TRAS (6)
#endif
#ifndef BSP_CFG_SDRAM_TRCD
#define BSP_CFG_SDRAM_TRCD (3)
#endif
#ifndef BSP_CFG_SDRAM_TRP
#define BSP_CFG_SDRAM_TRP (3)
#endif
#ifndef BSP_CFG_SDRAM_TWR
#define BSP_CFG_SDRAM_TWR (2)
#endif
#ifndef BSP_CFG_SDRAM_TCL
#define BSP_CFG_SDRAM_TCL (3)
#endif
#ifndef BSP_CFG_SDRAM_TRFC
#define BSP_CFG_SDRAM_TRFC (937)
#endif
#ifndef BSP_CFG_SDRAM_TREFW
#define BSP_CFG_SDRAM_TREFW (8)
#endif
#ifndef BSP_CFG_SDRAM_INIT_ARFI
#define BSP_CFG_SDRAM_INIT_ARFI (10)
#endif
#ifndef BSP_CFG_SDRAM_INIT_ARFC
#define BSP_CFG_SDRAM_INIT_ARFC (8)
#endif
#ifndef BSP_CFG_SDRAM_INIT_PRC
#define BSP_CFG_SDRAM_INIT_PRC (3)
#endif
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1)
#endif
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
#endif
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
#endif
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
Executable
+127
View File
@@ -0,0 +1,127 @@
/* generated configuration header file - do not edit */
#ifndef BSP_PIN_CFG_H_
#define BSP_PIN_CFG_H_
#include "r_ioport.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#define ENET_RMII_INT (BSP_IO_PORT_00_PIN_00)
#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_01)
#define GROVE2_AN102 (BSP_IO_PORT_00_PIN_02)
#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_03)
#define ARDUINO_A0_MIKROBUS_AN000 (BSP_IO_PORT_00_PIN_04)
#define GROVE2_AN001 (BSP_IO_PORT_00_PIN_05)
#define PMOD1_IRQ11 (BSP_IO_PORT_00_PIN_06)
#define ARDUINO_A004 (BSP_IO_PORT_00_PIN_07)
#define USER_S2 (BSP_IO_PORT_00_PIN_08)
#define SW1 (BSP_IO_PORT_00_PIN_09)
#define MIKROBUS_IRQ14 (BSP_IO_PORT_00_PIN_10)
#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
#define OSPI_DQ0 (BSP_IO_PORT_01_PIN_00)
#define OSPI_DQ3 (BSP_IO_PORT_01_PIN_01)
#define OSPI_DQ4 (BSP_IO_PORT_01_PIN_02)
#define OSPI_DQ2 (BSP_IO_PORT_01_PIN_03)
#define OSPI_CS (BSP_IO_PORT_01_PIN_04)
#define OSPI_INT (BSP_IO_PORT_01_PIN_05)
#define OSPI_RESET (BSP_IO_PORT_01_PIN_06)
#define LED3 (BSP_IO_PORT_01_PIN_07)
#define ETH_A_RMII_RMII_RXDV (BSP_IO_PORT_01_PIN_12)
#define ETH_A_LINKSTA (BSP_IO_PORT_01_PIN_14)
#define MPLX_CTRL (BSP_IO_PORT_01_PIN_15)
#define NMI (BSP_IO_PORT_02_PIN_00)
#define MD (BSP_IO_PORT_02_PIN_01)
#define CAN_STB (BSP_IO_PORT_02_PIN_07)
#define TDI (BSP_IO_PORT_02_PIN_08)
#define TDO (BSP_IO_PORT_02_PIN_09)
#define SWDIO (BSP_IO_PORT_02_PIN_10)
#define SWCLK (BSP_IO_PORT_02_PIN_11)
#define EXTAL (BSP_IO_PORT_02_PIN_12)
#define XTAL (BSP_IO_PORT_02_PIN_13)
#define ETH_A_RXER (BSP_IO_PORT_03_PIN_00)
#define ETH_A_RXD1 (BSP_IO_PORT_03_PIN_01)
#define ETH_A_RXD0 (BSP_IO_PORT_03_PIN_02)
#define ETH_A_REFCLK (BSP_IO_PORT_03_PIN_03)
#define ETH_A_TXD0 (BSP_IO_PORT_03_PIN_04)
#define ETH_A_TXD1 (BSP_IO_PORT_03_PIN_05)
#define ETH_A_TXEN (BSP_IO_PORT_03_PIN_06)
#define ETH_A_MDIO (BSP_IO_PORT_03_PIN_07)
#define ETH_A_MDC (BSP_IO_PORT_03_PIN_08)
#define ARDUINO_D0_MIKROBUS_RXD3 (BSP_IO_PORT_03_PIN_09)
#define ARDUINO_D1_MIKROBUS_TXD3 (BSP_IO_PORT_03_PIN_10)
#define CAN_RXD (BSP_IO_PORT_03_PIN_11)
#define CAN_TXD (BSP_IO_PORT_03_PIN_12)
#define I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic (BSP_IO_PORT_04_PIN_00)
#define I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic (BSP_IO_PORT_04_PIN_01)
#define ETH_B_MDIO (BSP_IO_PORT_04_PIN_02)
#define ETH_B_LINKSTA (BSP_IO_PORT_04_PIN_03)
#define ETH_B_RST_N (BSP_IO_PORT_04_PIN_04)
#define ETH_B_TXEN (BSP_IO_PORT_04_PIN_05)
#define ETH_B_TXD1 (BSP_IO_PORT_04_PIN_06)
#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07)
#define USBHS_VBUSEN (BSP_IO_PORT_04_PIN_08)
#define USBHS_OVRCURA (BSP_IO_PORT_04_PIN_09)
#define MISOB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_10)
#define MOSIB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_11)
#define RSPCKB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_12)
#define SSLB0_B_ARDUINO_D10_MIKROBUS (BSP_IO_PORT_04_PIN_13)
#define LED2 (BSP_IO_PORT_04_PIN_14)
#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00)
#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01)
#define MIKROBUS_RESET (BSP_IO_PORT_05_PIN_02)
#define PMOD2_7_IRQ1 (BSP_IO_PORT_05_PIN_08)
#define GROVE2_IIC_SDA1 (BSP_IO_PORT_05_PIN_11)
#define GROVE2_IIC_SCL1 (BSP_IO_PORT_05_PIN_12)
#define LED1 (BSP_IO_PORT_06_PIN_00)
#define ARDUINO_D5 (BSP_IO_PORT_06_PIN_01)
#define ARDUINO_D6 (BSP_IO_PORT_06_PIN_02)
#define ARDUINO_D9 (BSP_IO_PORT_06_PIN_03)
#define PMOD1_3_MISO0_RXD0_SCL0 (BSP_IO_PORT_06_PIN_09)
#define PMOD1_2_MOSI0_TXD0 (BSP_IO_PORT_06_PIN_10)
#define PMOD1_4_SCK0 (BSP_IO_PORT_06_PIN_11)
#define PMOD1_1_SSL0_CTS_RTS (BSP_IO_PORT_06_PIN_12)
#define PMOD1_1_CTS0 (BSP_IO_PORT_06_PIN_13)
#define PMOD1_9_GPIO (BSP_IO_PORT_06_PIN_14)
#define PMOD1_10_GPIO (BSP_IO_PORT_06_PIN_15)
#define ETH_B_TXD0 (BSP_IO_PORT_07_PIN_00)
#define ETH_B_REFCLK (BSP_IO_PORT_07_PIN_01)
#define ETH_B_RXD0 (BSP_IO_PORT_07_PIN_02)
#define ETH_B_RXD1 (BSP_IO_PORT_07_PIN_03)
#define ETH_B_RXER (BSP_IO_PORT_07_PIN_04)
#define ETH_B_RMII_RXDV (BSP_IO_PORT_07_PIN_05)
#define I3C_SDA0_PULLUP (BSP_IO_PORT_07_PIN_11)
#define OSPI_DQ5 (BSP_IO_PORT_08_PIN_00)
#define OSPI_DS (BSP_IO_PORT_08_PIN_01)
#define OSPI_DQ6 (BSP_IO_PORT_08_PIN_02)
#define OSPI_DQ1 (BSP_IO_PORT_08_PIN_03)
#define OSPI_DQ7 (BSP_IO_PORT_08_PIN_04)
#define OSPI_CK (BSP_IO_PORT_08_PIN_08)
#define PMOD2_8_RESET (BSP_IO_PORT_08_PIN_09)
#define PMOD2_9_GPIO (BSP_IO_PORT_08_PIN_10)
#define PMOD2_10_GPIO (BSP_IO_PORT_08_PIN_11)
#define ARDUINO_RESET (BSP_IO_PORT_08_PIN_12)
#define USBFS_P (BSP_IO_PORT_08_PIN_14)
#define USBFS_N (BSP_IO_PORT_08_PIN_15)
#define ARDUINO_D4 (BSP_IO_PORT_09_PIN_05)
#define ARDUINO_D2 (BSP_IO_PORT_09_PIN_06)
#define ARDUINO_D3_MIKROBUS_GTIOC13A (BSP_IO_PORT_09_PIN_07)
#define ARDUINO_D7 (BSP_IO_PORT_09_PIN_08)
#define ARDUINO_D8 (BSP_IO_PORT_09_PIN_09)
#define PMOD2_3_MISO2_RXD2 (BSP_IO_PORT_10_PIN_02)
#define PMOD2_2_MOSI2_TXD2 (BSP_IO_PORT_10_PIN_03)
#define PMOD2_4_SCK2 (BSP_IO_PORT_10_PIN_04)
#define PMOD2_1_CTS_RTS_SSL2 (BSP_IO_PORT_10_PIN_05)
#define PMOD2_1_CTS2 (BSP_IO_PORT_10_PIN_06)
#define PMOD1_8_RESET (BSP_IO_PORT_10_PIN_08)
#define JLOB_COMS_TX (BSP_IO_PORT_10_PIN_14)
#define JLOB_COMS_RX (BSP_IO_PORT_10_PIN_15)
#define I3C_SCL0_PULLUP (BSP_IO_PORT_11_PIN_00)
#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01)
extern const ioport_cfg_t g_bsp_pin_cfg; /* RA8M1 EK */
void BSP_PinConfigSecurityInit();
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif /* BSP_PIN_CFG_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
Executable
+13
View File
@@ -0,0 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#ifdef __cplusplus
}
#endif
#endif /* R_IOPORT_CFG_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h
Executable
+56
View File
@@ -0,0 +1,56 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */
#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL Mul x80-99|Mul x96|PLL Mul x96.00 */
#define BSP_CFG_PLL_FREQUENCY_HZ (960000000) /* PLL 960000000Hz */
#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */
#define BSP_CFG_PLL1P_FREQUENCY_HZ (480000000) /* PLL1P 480000000Hz */
#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_4) /* PLL1Q Div /4 */
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (240000000) /* PLL1Q 240000000Hz */
#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */
#define BSP_CFG_PLL1R_FREQUENCY_HZ (480000000) /* PLL1R 480000000Hz */
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL2 Mul x80-99|Mul x96|PLL2 Mul x96.00 */
#define BSP_CFG_PLL2_FREQUENCY_HZ (0) /* PLL2 0Hz */
#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL2P Div /2 */
#define BSP_CFG_PLL2P_FREQUENCY_HZ (0) /* PLL2P 0Hz */
#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (0) /* PLL2Q 0Hz */
#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */
#define BSP_CFG_PLL2R_FREQUENCY_HZ (0) /* PLL2R 0Hz */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SCICLK Disabled */
#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SPICLK Disabled */
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* I3CCLK Disabled */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* UCK Src: PLL1Q */
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* U60CK Src: PLL1P */
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */
#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */
#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* BCLK Div /4 */
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* FCLK Div /8 */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */
#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_4) /* SPICLK Div /4 */
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */
#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_3) /* I3CCLK Div /3 */
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCK Div /5 */
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_8) /* U60CK Div /8 */
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTASPICLK Div /4 */
#endif /* BSP_CLOCK_CFG_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c
Executable
+11
View File
@@ -0,0 +1,11 @@
/* generated common source file - do not edit */
#include "common_data.h"
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{
.p_api = &g_ioport_on_ioport,
.p_ctrl = &g_ioport_ctrl,
.p_cfg = &g_bsp_pin_cfg,
};
void g_common_init(void) {
}
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h
Executable
+20
View File
@@ -0,0 +1,20 @@
/* generated common header file - do not edit */
#ifndef COMMON_DATA_H_
#define COMMON_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
FSP_HEADER
#define IOPORT_CFG_NAME g_bsp_pin_cfg
#define IOPORT_CFG_OPEN R_IOPORT_Open
#define IOPORT_CFG_CTRL g_ioport_ctrl
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c
Executable
+275
View File
@@ -0,0 +1,275 @@
/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_00_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
},
{
.pin = BSP_IO_PORT_00_PIN_02,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_00_PIN_03,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_00_PIN_04,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_00_PIN_05,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_00_PIN_07,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_00_PIN_08,
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
},
{
.pin = BSP_IO_PORT_00_PIN_09,
.pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
},
{
.pin = BSP_IO_PORT_00_PIN_11,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_00_PIN_14,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_00_PIN_15,
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
},
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_01_PIN_02,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_01_PIN_03,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_01_PIN_04,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_01_PIN_05,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_01_PIN_06,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_01_PIN_07,
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
},
{
.pin = BSP_IO_PORT_02_PIN_09,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
},
{
.pin = BSP_IO_PORT_02_PIN_10,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
},
{
.pin = BSP_IO_PORT_02_PIN_11,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
},
{
.pin = BSP_IO_PORT_03_PIN_04,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
},
{
.pin = BSP_IO_PORT_03_PIN_05,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
},
{
.pin = BSP_IO_PORT_03_PIN_06,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
},
{
.pin = BSP_IO_PORT_03_PIN_07,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
},
{
.pin = BSP_IO_PORT_03_PIN_08,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
},
{
.pin = BSP_IO_PORT_04_PIN_07,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
},
{
.pin = BSP_IO_PORT_04_PIN_08,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
},
{
.pin = BSP_IO_PORT_04_PIN_09,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
},
{
.pin = BSP_IO_PORT_04_PIN_10,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
},
{
.pin = BSP_IO_PORT_04_PIN_11,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
},
{
.pin = BSP_IO_PORT_04_PIN_12,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
},
{
.pin = BSP_IO_PORT_04_PIN_13,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
},
{
.pin = BSP_IO_PORT_04_PIN_14,
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
},
{
.pin = BSP_IO_PORT_05_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
},
{
.pin = BSP_IO_PORT_05_PIN_01,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
},
{
.pin = BSP_IO_PORT_05_PIN_11,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
},
{
.pin = BSP_IO_PORT_05_PIN_12,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
},
{
.pin = BSP_IO_PORT_06_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
},
{
.pin = BSP_IO_PORT_08_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_08_PIN_01,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_08_PIN_02,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_08_PIN_03,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_08_PIN_04,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_08_PIN_08,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
},
{
.pin = BSP_IO_PORT_08_PIN_09,
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
},
{
.pin = BSP_IO_PORT_08_PIN_14,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
},
{
.pin = BSP_IO_PORT_08_PIN_15,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
},
{
.pin = BSP_IO_PORT_10_PIN_02,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
},
{
.pin = BSP_IO_PORT_10_PIN_03,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
},
{
.pin = BSP_IO_PORT_10_PIN_04,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
},
{
.pin = BSP_IO_PORT_10_PIN_05,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
},
{
.pin = BSP_IO_PORT_10_PIN_06,
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
},
{
.pin = BSP_IO_PORT_10_PIN_14,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
},
{
.pin = BSP_IO_PORT_10_PIN_15,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
},
{
.pin = BSP_IO_PORT_11_PIN_01,
.pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
};
#if BSP_TZ_SECURE_BUILD
void R_BSP_PinCfgSecurityInit(void);
/* Initialize SAR registers for secure pins. */
void R_BSP_PinCfgSecurityInit(void)
{
#if (2U == BSP_FEATURE_IOPORT_VERSION)
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#else
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
#endif
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
{
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
uint32_t port = port_pin >> 8U;
uint32_t pin = port_pin & 0xFFU;
pmsar[port] &= (uint16_t) ~(1U << pin);
}
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
#if (2U == BSP_FEATURE_IOPORT_VERSION)
R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
#else
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
#endif
}
}
#endif
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld
Executable
+823
View File
@@ -0,0 +1,823 @@
/*
Linker File for Renesas FSP
*/
INCLUDE memory_regions.ld
/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
/*
XIP_SECONDARY_SLOT_IMAGE = 1;
*/
QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
OPTION_SETTING_DATA_FLASH_S_START = DEFINED(OPTION_SETTING_DATA_FLASH_S_START) ? OPTION_SETTING_DATA_FLASH_S_START : 0;
OPTION_SETTING_DATA_FLASH_S_LENGTH = DEFINED(OPTION_SETTING_DATA_FLASH_S_LENGTH) ? OPTION_SETTING_DATA_FLASH_S_LENGTH : 0;
/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
* Bootloader images do not configure option settings because they are owned by the bootloader.
* FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
__bl_FSP_BOOTABLE_IMAGE = 1;
__bln_FSP_BOOTABLE_IMAGE = 1;
PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
USE_OPTION_SETTING_DATA_FLASH = PROJECT_SECURE_OR_FLAT && (OPTION_SETTING_DATA_FLASH_S_LENGTH != 0);
__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
(DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
__bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
__bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
__bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
__bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
FLASH_IMAGE_START;
LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
FLASH_LENGTH;
OPTION_SETTING_SAS_SIZE = 0x34;
OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
OPTION_SETTING_LENGTH == 0 ? 0 :
OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
/* Define memory regions. */
MEMORY
{
ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
OPTION_SETTING_DATA_FLASH_S (r) : ORIGIN = OPTION_SETTING_DATA_FLASH_S_START, LENGTH = OPTION_SETTING_DATA_FLASH_S_LENGTH
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be DEFINED in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
* __qspi_flash_start__
* __qspi_flash_end__
* __qspi_flash_code_size__
* __qspi_region_max_size__
* __qspi_region_start_address__
* __qspi_region_end_address__
* __ospi_device_0_start__
* __ospi_device_0_end__
* __ospi_device_0_code_size__
* __ospi_device_0_region_max_size__
* __ospi_device_0_region_start_address__
* __ospi_device_0_region_end_address__
* __ospi_device_1_start__
* __ospi_device_1_end__
* __ospi_device_1_code_size__
* __ospi_device_1_region_max_size__
* __ospi_device_1_region_start_address__
* __ospi_device_1_region_end_address__
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
__tz_FLASH_S = ABSOLUTE(FLASH_START);
__ROM_Start = .;
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
* space because ROM registers are at address 0x400 and there is very little space
* in between. */
KEEP(*(.fixed_vectors*))
KEEP(*(.application_vectors*))
__Vectors_End = .;
/* Some devices have a gap of code flash between the vector table and ROM Registers.
* The flash gap section allows applications to place code and data in this section. */
*(.flash_gap*)
/* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
/* Allocate flash write-boundary-aligned
* space for sce9 wrapped public keys for mcuboot if the module is used.
*/
KEEP(*(.mcuboot_sce9_key*))
*(.text*)
KEEP(*(.version))
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
__usb_dev_descriptor_start_fs = .;
KEEP(*(.usb_device_desc_fs*))
__usb_cfg_descriptor_start_fs = .;
KEEP(*(.usb_config_desc_fs*))
__usb_interface_descriptor_start_fs = .;
KEEP(*(.usb_interface_desc_fs*))
__usb_descriptor_end_fs = .;
__usb_dev_descriptor_start_hs = .;
KEEP(*(.usb_device_desc_hs*))
__usb_cfg_descriptor_start_hs = .;
KEEP(*(.usb_config_desc_hs*))
__usb_interface_descriptor_start_hs = .;
KEEP(*(.usb_interface_desc_hs*))
__usb_descriptor_end_hs = .;
KEEP(*(.eh_frame*))
__ROM_End = .;
} > FLASH = 0xFF
__Vectors_Size = __Vectors_End - __Vectors;
. = .;
__itcm_data_pre_location = .;
/* Initialized ITCM data. */
/* Aligned to FCACHE2 for RA8. */
.itcm_data : ALIGN(16)
{
/* Start of ITCM Secure Trustzone region. */
__tz_ITCM_S = ABSOLUTE(ITCM_START);
/* All ITCM data start */
__itcm_data_start = .;
KEEP(*(.itcm_data*))
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
. = ALIGN(8);
/* All ITCM data end */
__itcm_data_end = .;
/*
* Start of the ITCM Non-Secure Trustzone region.
* ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
*/
__tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
} > ITCM AT > FLASH = 0x00
/* Addresses exported for ITCM initialization. */
__itcm_data_init_start = LOADADDR(.itcm_data);
__itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
/* Restore location counter. */
/* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
/* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
. = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
__exidx_start = .;
/DISCARD/ :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
}
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
__tz_RAM_S = ORIGIN(RAM);
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
.fsp_dtc_vector_table (NOLOAD) :
{
. = ORIGIN(RAM);
*(.fsp_dtc_vector_table)
} > RAM
/* Initialized data section. */
.data :
{
__data_start__ = .;
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
*(vtable)
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
*(.data.*)
*(.data)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
. = .;
__dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
/* Initialized DTCM data. */
/* Aligned to FCACHE2 for RA8. */
.dtcm_data : ALIGN(16)
{
/* Start of DTCM Secure Trustzone region. */
__tz_DTCM_S = ABSOLUTE(DTCM_START);
/* Initialized DTCM data start */
__dtcm_data_start = .;
KEEP(*(.dtcm_data*))
/* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
. = ALIGN(8);
/* Initialized DTCM data end */
__dtcm_data_end = .;
} > DTCM AT > FLASH = 0x00
. = __dtcm_data_end;
/* Uninitialized DTCM data. */
/* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
.dtcm_bss ALIGN(8) (NOLOAD) :
{
/* Uninitialized DTCM data start */
__dtcm_bss_start = .;
KEEP(*(.dtcm_bss*))
/* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
. = ALIGN(8);
/* Uninitialized DTCM data end */
__dtcm_bss_end = .;
/*
* Start of the DTCM Non-Secure Trustzone region.
* DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
*/
__tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
} > DTCM
/* Addresses exported for DTCM initialization. */
__dtcm_data_init_start = LOADADDR(.dtcm_data);
__dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
/* Restore location counter. */
/* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
/* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
. = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
/* TrustZone Secure Gateway Stubs Section */
/* Store location counter for SPI non-retentive sections. */
sgstubs_pre_location = .;
/* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
.gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
{
__FLASH_NSC_START = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
_start_sg = .;
*(.gnu.sgstubs*)
. = ALIGN(32);
_end_sg = .;
} > FLASH
__tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
__tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
/* QSPI_FLASH section to be downloaded via debugger */
.qspi_flash :
{
__qspi_flash_start__ = .;
KEEP(*(.qspi_flash*))
KEEP(*(.code_in_qspi*))
__qspi_flash_end__ = .;
} > QSPI_FLASH
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
__qspi_flash_code_addr__ = sgstubs_pre_location;
.qspi_non_retentive : AT(__qspi_flash_code_addr__)
{
__qspi_non_retentive_start__ = .;
KEEP(*(.qspi_non_retentive*))
__qspi_non_retentive_end__ = .;
} > QSPI_FLASH
__qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
__qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
__qspi_region_start_address__ = __qspi_flash_start__;
__qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
/* Support for OctaRAM */
.OSPI_DEVICE_0_NO_LOAD (NOLOAD):
{
. = ALIGN(4);
__ospi_device_0_start__ = .;
*(.ospi_device_0_no_load*)
. = ALIGN(4);
__ospi_device_0_end__ = .;
} > OSPI_DEVICE_0_RAM
.OSPI_DEVICE_1_NO_LOAD (NOLOAD):
{
. = ALIGN(4);
__ospi_device_1_start__ = .;
*(.ospi_device_1_no_load*)
. = ALIGN(4);
__ospi_device_1_end__ = .;
} > OSPI_DEVICE_1_RAM
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
/* OSPI_DEVICE_0 section to be downloaded via debugger */
.OSPI_DEVICE_0 :
{
__ospi_device_0_start__ = .;
KEEP(*(.ospi_device_0*))
KEEP(*(.code_in_ospi_device_0*))
__ospi_device_0_end__ = .;
} > OSPI_DEVICE_0
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
__ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
.ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
{
__ospi_device_0_non_retentive_start__ = .;
KEEP(*(.ospi_device_0_non_retentive*))
__ospi_device_0_non_retentive_end__ = .;
} > OSPI_DEVICE_0
__ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
__ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
__ospi_device_0_region_start_address__ = __ospi_device_0_start__;
__ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
__tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
__tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
/* OSPI_DEVICE_1 section to be downloaded via debugger */
.OSPI_DEVICE_1 :
{
__ospi_device_1_start__ = .;
KEEP(*(.ospi_device_1*))
KEEP(*(.code_in_ospi_device_1*))
__ospi_device_1_end__ = .;
} > OSPI_DEVICE_1
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
__ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
.ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
{
__ospi_device_1_non_retentive_start__ = .;
KEEP(*(.ospi_device_1_non_retentive*))
__ospi_device_1_non_retentive_end__ = .;
} > OSPI_DEVICE_1
__ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
__ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
__ospi_device_1_region_start_address__ = __ospi_device_1_start__;
__ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
__tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
.noinit (NOLOAD):
{
. = ALIGN(4);
__noinit_start = .;
KEEP(*(.noinit*))
. = ALIGN(8);
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
KEEP(*(.heap.*))
__noinit_end = .;
} > RAM
. = .;
__nocache_pre_location = .;
.nocache ALIGN(32) (NOLOAD):
{
__nocache_start = .;
KEEP(*(.nocache))
. = ALIGN(32);
__nocache_end = .;
} > RAM
. = (SIZEOF(.nocache) > 0) ? __nocache_end : __nocache_pre_location;
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (NOLOAD):
{
. = ALIGN(8);
__HeapBase = .;
/* Place the STD heap here. */
KEEP(*(.heap))
__HeapLimit = .;
} > RAM
/* Stacks are stored in this section. */
.stack_dummy (NOLOAD):
{
. = ALIGN(8);
__StackLimit = .;
/* Main stack */
KEEP(*(.stack))
__StackTop = .;
/* Thread stacks */
KEEP(*(.stack*))
__StackTopAll = .;
} > RAM
PROVIDE(__stack = __StackTopAll);
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
at run time for things such as ThreadX memory pool allocations. */
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
/* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
* If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
__RAM_NSC_START = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
/* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
* RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
* specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
__tz_RAM_N = DEFINED(FLASH_BOOTLOADER_LENGTH) ? (RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH) : DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_NSC_START, 8192);
/* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
* The EDMAC is a non-secure bus master and can only access non-secure RAM. */
.ns_buffer (NOLOAD):
{
/* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
. = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
KEEP(*(.ns_buffer*))
} > RAM
/* Data flash. */
.data_flash :
{
. = ORIGIN(DATA_FLASH);
__tz_DATA_FLASH_S = .;
__Data_Flash_Start = .;
KEEP(*(.data_flash*))
__Data_Flash_End = .;
__tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
} > DATA_FLASH
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
__tz_SDRAM_S = ORIGIN(SDRAM);
/* SDRAM */
.sdram (NOLOAD):
{
__SDRAM_Start = .;
KEEP(*(.sdram*))
KEEP(*(.frame*))
__SDRAM_End = .;
} > SDRAM
. = .;
__nocache_sdram_pre_location = .;
.nocache_sdram ALIGN(32) (NOLOAD):
{
__nocache_sdram_start = .;
KEEP(*(.nocache_sdram))
. = ALIGN(32);
__nocache_sdram_end = .;
} > SDRAM
. = (SIZEOF(.nocache_sdram) > 0) ? __nocache_sdram_end : __nocache_sdram_pre_location;
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
__tz_SDRAM_N = __SDRAM_End;
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
__tz_ID_CODE_S = ORIGIN(ID_CODE);
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
* Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
* memory region between TrustZone projects. */
__tz_ID_CODE_N = __tz_ID_CODE_S;
.id_code :
{
__ID_Code_Start = .;
KEEP(*(.id_code*))
__ID_Code_End = .;
} > ID_CODE
/* Symbol required for RA Configuration tool. */
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
.option_setting_ofs :
{
__OPTION_SETTING_OFS_Start = .;
KEEP(*(.option_setting_ofs0))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
KEEP(*(.option_setting_ofs2))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
KEEP(*(.option_setting_dualsel))
__OPTION_SETTING_OFS_End = .;
} > OPTION_SETTING_OFS = 0xFF
.option_setting_sas :
{
__OPTION_SETTING_SAS_Start = .;
KEEP(*(.option_setting_sas))
__OPTION_SETTING_SAS_End = .;
} > OPTION_SETTING_SAS = 0xFF
/* Symbol required for RA Configuration tool. */
__tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
.option_setting_ns :
{
__OPTION_SETTING_NS_Start = .;
KEEP(*(.option_setting_ofs1))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_ofs3))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_banksel))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_bps0))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_bps1))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_bps2))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_bps3))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_pbps0))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_pbps1))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_pbps2))
. = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
KEEP(*(.option_setting_pbps3))
__OPTION_SETTING_NS_End = .;
} > OPTION_SETTING = 0xFF
/* Symbol required for RA Configuration tool. */
__tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
.option_setting_s :
{
__OPTION_SETTING_S_Start = .;
KEEP(*(.option_setting_ofs1_sec))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_ofs3_sec))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_banksel_sec))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sec0))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sec1))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sec2))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sec3))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_pbps_sec0))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_pbps_sec1))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_pbps_sec2))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_pbps_sec3))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_ofs1_sel))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_ofs3_sel))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_banksel_sel))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sel0))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sel1))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sel2))
. = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
KEEP(*(.option_setting_bps_sel3))
__OPTION_SETTING_S_End = .;
} > OPTION_SETTING_S = 0xFF
/* Symbol required for RA Configuration tool. */
__tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
/* Symbol required for RA Configuration tool. */
__tz_OPTION_SETTING_DATA_FLASH_S_S = ORIGIN(OPTION_SETTING_DATA_FLASH_S);
.option_setting_data_flash_s :
{
__OPTION_SETTING_DATA_FLASH_S_Start = .;
KEEP(*(.option_setting_data_flash_fsblctrl0))
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x04 : __OPTION_SETTING_DATA_FLASH_S_Start;
KEEP(*(.option_setting_data_flash_fsblctrl1))
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x08 : __OPTION_SETTING_DATA_FLASH_S_Start;
KEEP(*(.option_setting_data_flash_fsblctrl2))
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x0C : __OPTION_SETTING_DATA_FLASH_S_Start;
KEEP(*(.option_setting_data_flash_sacc0))
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x10 : __OPTION_SETTING_DATA_FLASH_S_Start;
KEEP(*(.option_setting_data_flash_sacc1))
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x14 : __OPTION_SETTING_DATA_FLASH_S_Start;
KEEP(*(.option_setting_data_flash_samr))
. = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x2E0 : __OPTION_SETTING_DATA_FLASH_S_Start;
KEEP(*(.option_setting_data_flash_hoemrtpk))
__OPTION_SETTING_DATA_FLASH_S_End = .;
} > OPTION_SETTING_DATA_FLASH_S = 0xFF
/* Symbol required for RA Configuration tool. */
__tz_OPTION_SETTING_DATA_FLASH_S_N = __OPTION_SETTING_DATA_FLASH_S_End;
}
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld
Executable
+30
View File
@@ -0,0 +1,30 @@
/* generated memory regions file - do not edit */
RAM_START = 0x22000000;
RAM_LENGTH = 0xE0000;
FLASH_START = 0x02000000;
FLASH_LENGTH = 0x1F8000;
DATA_FLASH_START = 0x27000000;
DATA_FLASH_LENGTH = 0x3000;
OPTION_SETTING_START = 0x0300A100;
OPTION_SETTING_LENGTH = 0x100;
OPTION_SETTING_S_START = 0x0300A200;
OPTION_SETTING_S_LENGTH = 0x100;
OPTION_SETTING_DATA_FLASH_S_START = 0x27030080;
OPTION_SETTING_DATA_FLASH_S_LENGTH = 0x800;
ID_CODE_START = 0x00000000;
ID_CODE_LENGTH = 0x0;
SDRAM_START = 0x68000000;
SDRAM_LENGTH = 0x8000000;
QSPI_FLASH_START = 0x60000000;
QSPI_FLASH_LENGTH = 0x0;
OSPI_DEVICE_0_START = 0x80000000;
OSPI_DEVICE_0_LENGTH = 0x10000000;
OSPI_DEVICE_1_START = 0x90000000;
OSPI_DEVICE_1_LENGTH = 0x10000000;
ITCM_START = 0x00000000;
ITCM_LENGTH = 0x10000;
DTCM_START = 0x20000000;
DTCM_LENGTH = 0x10000;
NS_OFFSET_START = 0x10000000;
NS_OFFSET_LENGTH = 0x0;
components/espressif__tinyusb/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml
Executable
+680
View File
@@ -0,0 +1,680 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="9">
<generalSettings>
<option key="#Board#" value="board.ra8m1ek"/>
<option key="CPU" value="RA8M1"/>
<option key="Core" value="CM85"/>
<option key="#TargetName#" value="R7FA8M1AHECBD"/>
<option key="#TargetARCHITECTURE#" value="cortex-m85"/>
<option key="#DeviceCommand#" value="R7FA8M1AH"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA8M1AHECBD.pincfg"/>
<option key="#FSPVersion#" value="5.6.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra8m1_ek##"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.renesas.cdt.managedbuild.gnuarm.toolchain."/>
</generalSettings>
<raBspConfiguration>
<config id="config.bsp.ra8m1.R7FA8M1AHECBD">
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
<property id="config.bsp.rom_size_bytes_hidden" value="2064384"/>
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
<property id="config.bsp.irq_count_hidden" value="96"/>
</config>
<config id="config.bsp.ra8m1">
<property id="config.bsp.series" value="config.bsp.series.value"/>
</config>
<config id="config.bsp.ra8m1.fsp">
<property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
<property id="config.bsp.fsp.sdram.enabled" value="config.bsp.fsp.sdram.enabled.disabled"/>
<property id="config.bsp.fsp.sdram.tras" value="config.bsp.fsp.sdram.tras.6"/>
<property id="config.bsp.fsp.sdram.trcd" value="config.bsp.fsp.sdram.trcd.3"/>
<property id="config.bsp.fsp.sdram.trp" value="config.bsp.fsp.sdram.trp.3"/>
<property id="config.bsp.fsp.sdram.twr" value="config.bsp.fsp.sdram.twr.2"/>
<property id="config.bsp.fsp.sdram.tcl" value="config.bsp.fsp.sdram.tcl.3"/>
<property id="config.bsp.fsp.sdram.trfc" value="937"/>
<property id="config.bsp.fsp.sdram.trefw" value="config.bsp.fsp.sdram.trefw.8"/>
<property id="config.bsp.fsp.sdram.arfi" value="config.bsp.fsp.sdram.arfi.10"/>
<property id="config.bsp.fsp.sdram.arfc" value="config.bsp.fsp.sdram.arfc.8"/>
<property id="config.bsp.fsp.sdram.prc" value="config.bsp.fsp.sdram.prc.3"/>
<property id="config.bsp.fsp.sdram.addr_shift" value="config.bsp.fsp.sdram.addr_shift.9"/>
<property id="config.bsp.fsp.sdram.endian_mode" value="config.bsp.fsp.sdram.endian_mode.little"/>
<property id="config.bsp.fsp.sdram.continuous_access_mode" value="config.bsp.fsp.sdram.continuous_access_mode.enabled"/>
<property id="config.bsp.fsp.sdram.bus_width" value="config.bsp.fsp.sdram.bus_width.16"/>
<property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
<property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
<property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
<property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
<property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
<property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramsa0" value="config.bsp.fsp.tz.sramsar.sramsa0.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramsa1" value="config.bsp.fsp.tz.sramsar.sramsa1.both"/>
<property id="config.bsp.fsp.tz.sramsar.stbramsa" value="config.bsp.fsp.tz.sramsar.stbramsa.both"/>
<property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
<property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
<property id="config.bsp.fsp.tz.bussarc" value="config.bsp.fsp.tz.bussarc.both"/>
<property id="config.bsp.fsp.tz.banksel_sel" value="config.bsp.fsp.tz.banksel_sel.both"/>
<property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0_level" value="config.bsp.fsp.OFS1_SEL.voltage_detection0_level.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.start" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.start.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1_SEL.voltage_detection0.low_power_consumption.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.swdbg" value="config.bsp.fsp.OFS1_SEL.swdbg.secure"/>
<property id="config.bsp.fsp.OFS1_SEL.initeccen" value="config.bsp.fsp.OFS1_SEL.initeccen.secure"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.160"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption" value="config.bsp.fsp.OFS1.voltage_detection0.low_power_consumption.disabled"/>
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
<property id="config.bsp.fsp.OFS1.swdbg" value="config.bsp.fsp.OFS1.swdbg.disabled"/>
<property id="config.bsp.fsp.OFS1.initeccen" value="config.bsp.fsp.OFS1.initeccen.disabled"/>
<property id="config.bsp.fsp.OFS2.dcdc" value="config.bsp.fsp.OFS2.dcdc.enabled"/>
<property id="config.bsp.fsp.BPS.BPS0" value=""/>
<property id="config.bsp.fsp.BPS.BPS1" value=""/>
<property id="config.bsp.fsp.BPS.BPS2" value=""/>
<property id="config.bsp.fsp.BPS.BPS3" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS3" value=""/>
<property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLEN" value="config.bsp.fsp.FSBLCTRL0.FSBLEN.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPSW.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS" value="config.bsp.fsp.FSBLCTRL0.FSBLSKIPDS.disabled"/>
<property id="config.bsp.fsp.FSBLCTRL0.FSBLCLK" value="config.bsp.fsp.FSBLCTRL0.FSBLCLK.240"/>
<property id="config.bsp.fsp.FSBLCTRL1.FSBLEXMD" value="config.bsp.fsp.FSBLCTRL1.FSBLEXMD.secure_report"/>
<property id="config.bsp.fsp.FSBLCTRL2.PORTPN" value="config.bsp.fsp.FSBLCTRL2.PORTPN.15"/>
<property id="config.bsp.fsp.FSBLCTRL2.PORTGN" value="config.bsp.fsp.FSBLCTRL2.PORTGN.reserved"/>
<property id="config.bsp.fsp.SACC0" value="0xFFFFFFFF"/>
<property id="config.bsp.fsp.SACC1" value="0xFFFFFFFF"/>
<property id="config.bsp.fsp.SAMR" value="0xFFFFFFFF"/>
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
<property id="config.bsp.fsp.clock_settling_delay" value="config.bsp.fsp.clock_settling_delay.enabled"/>
<property id="config.bsp.fsp.sleep_mode_delays" value="config.bsp.fsp.sleep_mode_delays.enabled"/>
<property id="config.bsp.fsp.rtos_idle_sleep" value="config.bsp.fsp.rtos_idle_sleep.disabled"/>
<property id="config.bsp.fsp.mstp_change_delays" value="config.bsp.fsp.mstp_change_delays.enabled"/>
<property id="config.bsp.fsp.settling_delay_us" value="150"/>
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/>
<property id="config.bsp.fsp.mcu.sci_b_uart.max_baud" value="30000000"/>
<property id="config.bsp.fsp.mcu.sci_b_uart.ctspen_channels" value="0x021F"/>
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/>
<property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/>
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="60000000"/>
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
<property id="config.bsp.fsp.mcu.iic_master.fastplus_channels" value="0x3"/>
<property id="config.bsp.fsp.mcu.iic_slave.rate.rate_fastplus" value="1"/>
<property id="config.bsp.fsp.mcu.iic_slave.fastplus_channels" value="0x3"/>
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0x3FFF"/>
<property id="config.bsp.fsp.mcu.canfd.num_channels" value="2"/>
<property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="2"/>
<property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="1216"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules" value="32"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="16"/>
<property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="8"/>
<property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="32767"/>
<property id="config.bsp.fsp.mcu.sci_b_lin.max_baud" value="7500000"/>
<property id="config.bsp.fsp.dcache" value="config.bsp.fsp.dcache.disabled"/>
</config>
<config id="config.bsp.ra">
<property id="config.bsp.common.main" value="0x1000"/>
<property id="config.bsp.common.heap" value="0x1000"/>
<property id="config.bsp.common.vcc" value="3300"/>
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
</config>
</raBspConfiguration>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.96_00"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll1p.div" option="board.clock.pll1p.div.2"/>
<node id="board.clock.pll1p.display" option="board.clock.pll1p.display.value"/>
<node id="board.clock.pll1q.div" option="board.clock.pll1q.div.4"/>
<node id="board.clock.pll1q.display" option="board.clock.pll1q.display.value"/>
<node id="board.clock.pll1r.div" option="board.clock.pll1r.div.2"/>
<node id="board.clock.pll1r.display" option="board.clock.pll1r.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.96_00"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.pll2p.div" option="board.clock.pll2p.div.2"/>
<node id="board.clock.pll2p.display" option="board.clock.pll2p.display.value"/>
<node id="board.clock.pll2q.div" option="board.clock.pll2q.div.2"/>
<node id="board.clock.pll2q.display" option="board.clock.pll2q.display.value"/>
<node id="board.clock.pll2r.div" option="board.clock.pll2r.div.2"/>
<node id="board.clock.pll2r.display" option="board.clock.pll2r.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll1p"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.sciclk.source" option="board.clock.sciclk.source.disabled"/>
<node id="board.clock.spiclk.source" option="board.clock.spiclk.source.disabled"/>
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
<node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/>
<node id="board.clock.uck.source" option="board.clock.uck.source.pll1q"/>
<node id="board.clock.u60ck.source" option="board.clock.u60ck.source.pll1p"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.cpuclk.div" option="board.clock.cpuclk.div.1"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.4"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.8"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.8"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.4"/>
<node id="board.clock.pclke.div" option="board.clock.pclke.div.2"/>
<node id="board.clock.sdclkout.enable" option="board.clock.sdclkout.enable.enabled"/>
<node id="board.clock.bclk.div" option="board.clock.bclk.div.4"/>
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.8"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.sciclk.div" option="board.clock.sciclk.div.4"/>
<node id="board.clock.spiclk.div" option="board.clock.spiclk.div.4"/>
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.8"/>
<node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.3"/>
<node id="board.clock.uck.div" option="board.clock.uck.div.5"/>
<node id="board.clock.u60ck.div" option="board.clock.u60ck.div.8"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.4"/>
<node id="board.clock.cpuclk.display" option="board.clock.cpuclk.display.value"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.pclke.display" option="board.clock.pclke.display.value"/>
<node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.sciclk.display" option="board.clock.sciclk.display.value"/>
<node id="board.clock.spiclk.display" option="board.clock.spiclk.display.value"/>
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
<node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/>
<node id="board.clock.uck.display" option="board.clock.uck.display.value"/>
<node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
</raClockConfiguration>
<raComponentSelection>
<component apiversion="" class="Projects" condition="" group="all" subgroup="baremetal_blinky" variant="" vendor="Renesas" version="5.6.0">
<description>Simple application that blinks an LED. No RTOS included.</description>
<originalPack>Renesas.RA_baremetal_blinky.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.6.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.6.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.6.0">
<description>Arm CMSIS Version 6 - Core (M)</description>
<originalPack>Arm.CMSIS6.6.1.0+fsp.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="ra8m1_ek" variant="" vendor="Renesas" version="5.6.0">
<description>RA8M1-EK Board Support Files</description>
<originalPack>Renesas.RA_board_ra8m1_ek.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="R7FA8M1AHECBD" vendor="Renesas" version="5.6.0">
<description>Board support package for R7FA8M1AHECBD</description>
<originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="device" variant="" vendor="Renesas" version="5.6.0">
<description>Board support package for RA8M1</description>
<originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="fsp" variant="" vendor="Renesas" version="5.6.0">
<description>Board support package for RA8M1 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra8m1" subgroup="events" variant="" vendor="Renesas" version="5.6.0">
<description>Board support package for RA8M1 - Events</description>
<originalPack>Renesas.RA_mcu_ra8m1.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_usb_basic" variant="" vendor="Renesas" version="5.6.0">
<description>USB Basic</description>
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_usb_pcdc" variant="" vendor="Renesas" version="5.6.0">
<description>USB Peripheral Communications Device Class</description>
<originalPack>Renesas.RA.5.6.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
<raIcuConfiguration/>
<raModuleConfiguration>
<module id="module.driver.ioport_on_ioport.0">
<property id="module.driver.ioport.name" value="g_ioport"/>
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
</module>
<module id="module.driver.pcdc_on_usb.216998869">
<property id="module.driver.pcdc.name" value="g_pcdc0"/>
</module>
<module id="module.driver.basic_on_usb.877233012">
<property id="module.driver.basic.name" value="g_basic1"/>
<property id="module.driver.usb_basic.usb_mode" value="module.driver.usb_basic.usb_mode.host"/>
<property id="module.driver.usb_basic.usb_speed" value="module.driver.usb_basic.usb_speed.hs"/>
<property id="module.driver.usb_basic.usb_modulenumber" value="module.driver.usb_basic.usb_modulenumber.1"/>
<property id="module.driver.usb_basic.usb_classtype" value="module.driver.usb_basic.usb_classtype.pcdc"/>
<property id="module.driver.usb_basic.p_usb_reg" value="g_usb_descriptor"/>
<property id="module.driver.usb_basic.complience_cb" value="NULL"/>
<property id="module.driver.usb_basic.ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.usb_basic.ipl_r" value="board.icu.common.irq.priority12"/>
<property id="module.driver.usb_basic.ipl_d0" value="board.icu.common.irq.priority12"/>
<property id="module.driver.usb_basic.ipl_d1" value="board.icu.common.irq.priority12"/>
<property id="module.driver.usb_basic.hsipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.usb_basic.hsipl_d0" value="board.icu.common.irq.priority12"/>
<property id="module.driver.usb_basic.hsipl_d1" value="board.icu.common.irq.priority12"/>
<property id="module.driver.usb_basic.rtos_callback" value="NULL"/>
<property id="module.driver.usb_basic.other_context" value="NULL"/>
</module>
<context id="_hal.0">
<stack module="module.driver.ioport_on_ioport.0"/>
<stack module="module.driver.pcdc_on_usb.216998869">
<stack module="module.driver.basic_on_usb.877233012" requires="module.driver.basic_on_usb.requires.basic"/>
</stack>
</context>
<config id="config.driver.usb_basic">
<property id="config.driver.usb_basic.param_checking_enable" value="config.driver.usb_basic.param_checking_enable.bsp"/>
<property id="config.driver.usb_basic.pll_clock_frequency" value="config.driver.usb_basic.pll_clock_frequency.20mhz"/>
<property id="config.driver.usb_basic.buswait" value="config.driver.usb_basic.buswait.7"/>
<property id="config.driver.usb_basic.bc_function" value="config.driver.usb_basic.bc_function.enable"/>
<property id="config.driver.usb_basic.power_source" value="config.driver.usb_basic.power_source.high"/>
<property id="config.driver.usb_basic.dcp_function" value="config.driver.usb_basic.dcp_function.disable"/>
<property id="config.driver.usb_basic.request" value="config.driver.usb_basic.request.enable"/>
<property id="config.driver.usb_basic.dblb" value="config.driver.usb_basic.dblb.enable"/>
<property id="config.driver.usb_basic.cntmd" value="config.driver.usb_basic.cntmd.disable"/>
<property id="config.driver.usb_basic.ldo_regulator" value="config.driver.usb_basic.ldo_regulator.disable"/>
<property id="config.driver.usb_basic.type_c" value="config.driver.usb_basic.type_c.disable"/>
<property id="config.driver.usb_basic.dma" value="config.driver.usb_basic.dma.disable"/>
<property id="config.driver.usb_basic.source_address" value="config.driver.usb_basic.source_address.none"/>
<property id="config.driver.usb_basic.dest_address" value="config.driver.usb_basic.dest_address.none"/>
<property id="config.driver.usb_basic.compliance_mode" value="config.driver.usb_basic.compliance_mode.disable"/>
<property id="config.driver.usb_basic.tpl_table" value="NULL"/>
</config>
<config id="config.driver.usb_pcdc">
<property id="config.driver.usb_pcdc.bulk_in" value="config.driver.usb_pcdc.bulk_in.pipe4"/>
<property id="config.driver.usb_pcdc.bulk_out" value="config.driver.usb_pcdc.bulk_out.pipe5"/>
<property id="config.driver.usb_pcdc.int_in" value="config.driver.usb_pcdc.int_in.pipe6"/>
</config>
<config id="config.driver.usb_pcdc_class"/>
<config id="config.driver.ioport">
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
</config>
</raModuleConfiguration>
<raPinConfiguration>
<symbolicName propertyId="p000.symbolic_name" value="ENET_RMII_INT"/>
<symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A3"/>
<symbolicName propertyId="p002.symbolic_name" value="GROVE2_AN102"/>
<symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A1"/>
<symbolicName propertyId="p004.symbolic_name" value="ARDUINO_A0_MIKROBUS_AN000"/>
<symbolicName propertyId="p005.symbolic_name" value="GROVE2_AN001"/>
<symbolicName propertyId="p006.symbolic_name" value="PMOD1_IRQ11"/>
<symbolicName propertyId="p007.symbolic_name" value="ARDUINO_A004"/>
<symbolicName propertyId="p008.symbolic_name" value="USER_S2"/>
<symbolicName propertyId="p009.symbolic_name" value="SW1"/>
<symbolicName propertyId="p010.symbolic_name" value="MIKROBUS_IRQ14"/>
<symbolicName propertyId="p014.symbolic_name" value="ARDUINO_A4"/>
<symbolicName propertyId="p015.symbolic_name" value="ARDUINO_A5"/>
<symbolicName propertyId="p100.symbolic_name" value="OSPI_DQ0"/>
<symbolicName propertyId="p101.symbolic_name" value="OSPI_DQ3"/>
<symbolicName propertyId="p102.symbolic_name" value="OSPI_DQ4"/>
<symbolicName propertyId="p103.symbolic_name" value="OSPI_DQ2"/>
<symbolicName propertyId="p104.symbolic_name" value="OSPI_CS"/>
<symbolicName propertyId="p105.symbolic_name" value="OSPI_INT"/>
<symbolicName propertyId="p106.symbolic_name" value="OSPI_RESET"/>
<symbolicName propertyId="p107.symbolic_name" value="LED3"/>
<symbolicName propertyId="p112.symbolic_name" value="ETH_A_RMII_RMII_RXDV"/>
<symbolicName propertyId="p114.symbolic_name" value="ETH_A_LINKSTA"/>
<symbolicName propertyId="p115.symbolic_name" value="MPLX_CTRL"/>
<symbolicName propertyId="p200.symbolic_name" value="NMI"/>
<symbolicName propertyId="p201.symbolic_name" value="MD"/>
<symbolicName propertyId="p207.symbolic_name" value="CAN_STB"/>
<symbolicName propertyId="p208.symbolic_name" value="TDI"/>
<symbolicName propertyId="p209.symbolic_name" value="TDO"/>
<symbolicName propertyId="p210.symbolic_name" value="SWDIO"/>
<symbolicName propertyId="p211.symbolic_name" value="SWCLK"/>
<symbolicName propertyId="p212.symbolic_name" value="EXTAL"/>
<symbolicName propertyId="p213.symbolic_name" value="XTAL"/>
<symbolicName propertyId="p300.symbolic_name" value="ETH_A_RXER"/>
<symbolicName propertyId="p301.symbolic_name" value="ETH_A_RXD1"/>
<symbolicName propertyId="p302.symbolic_name" value="ETH_A_RXD0"/>
<symbolicName propertyId="p303.symbolic_name" value="ETH_A_REFCLK"/>
<symbolicName propertyId="p304.symbolic_name" value="ETH_A_TXD0"/>
<symbolicName propertyId="p305.symbolic_name" value="ETH_A_TXD1"/>
<symbolicName propertyId="p306.symbolic_name" value="ETH_A_TXEN"/>
<symbolicName propertyId="p307.symbolic_name" value="ETH_A_MDIO"/>
<symbolicName propertyId="p308.symbolic_name" value="ETH_A_MDC"/>
<symbolicName propertyId="p309.symbolic_name" value="ARDUINO_D0_MIKROBUS_RXD3"/>
<symbolicName propertyId="p310.symbolic_name" value="ARDUINO_D1_MIKROBUS_TXD3"/>
<symbolicName propertyId="p311.symbolic_name" value="CAN_RXD"/>
<symbolicName propertyId="p312.symbolic_name" value="CAN_TXD"/>
<symbolicName propertyId="p400.symbolic_name" value="I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic"/>
<symbolicName propertyId="p401.symbolic_name" value="I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic"/>
<symbolicName propertyId="p402.symbolic_name" value="ETH_B_MDIO"/>
<symbolicName propertyId="p403.symbolic_name" value="ETH_B_LINKSTA"/>
<symbolicName propertyId="p404.symbolic_name" value="ETH_B_RST_N"/>
<symbolicName propertyId="p405.symbolic_name" value="ETH_B_TXEN"/>
<symbolicName propertyId="p406.symbolic_name" value="ETH_B_TXD1"/>
<symbolicName propertyId="p407.symbolic_name" value="USBFS_VBUS"/>
<symbolicName propertyId="p408.symbolic_name" value="USBHS_VBUSEN"/>
<symbolicName propertyId="p409.symbolic_name" value="USBHS_OVRCURA"/>
<symbolicName propertyId="p410.symbolic_name" value="MISOB_B_ARDUINO_MIKROBUS"/>
<symbolicName propertyId="p411.symbolic_name" value="MOSIB_B_ARDUINO_MIKROBUS"/>
<symbolicName propertyId="p412.symbolic_name" value="RSPCKB_B_ARDUINO_MIKROBUS"/>
<symbolicName propertyId="p413.symbolic_name" value="SSLB0_B_ARDUINO_D10_MIKROBUS"/>
<symbolicName propertyId="p414.symbolic_name" value="LED2"/>
<symbolicName propertyId="p500.symbolic_name" value="USBFS_VBUS_EN"/>
<symbolicName propertyId="p501.symbolic_name" value="USBFS_OVERCURA"/>
<symbolicName propertyId="p502.symbolic_name" value="MIKROBUS_RESET"/>
<symbolicName propertyId="p508.symbolic_name" value="PMOD2_7_IRQ1"/>
<symbolicName propertyId="p511.symbolic_name" value="GROVE2_IIC_SDA1"/>
<symbolicName propertyId="p512.symbolic_name" value="GROVE2_IIC_SCL1"/>
<symbolicName propertyId="p600.symbolic_name" value="LED1"/>
<symbolicName propertyId="p601.symbolic_name" value="ARDUINO_D5"/>
<symbolicName propertyId="p602.symbolic_name" value="ARDUINO_D6"/>
<symbolicName propertyId="p603.symbolic_name" value="ARDUINO_D9"/>
<symbolicName propertyId="p609.symbolic_name" value="PMOD1_3_MISO0_RXD0_SCL0"/>
<symbolicName propertyId="p610.symbolic_name" value="PMOD1_2_MOSI0_TXD0"/>
<symbolicName propertyId="p611.symbolic_name" value="PMOD1_4_SCK0"/>
<symbolicName propertyId="p612.symbolic_name" value="PMOD1_1_SSL0_CTS_RTS"/>
<symbolicName propertyId="p613.symbolic_name" value="PMOD1_1_CTS0"/>
<symbolicName propertyId="p614.symbolic_name" value="PMOD1_9_GPIO"/>
<symbolicName propertyId="p615.symbolic_name" value="PMOD1_10_GPIO"/>
<symbolicName propertyId="p700.symbolic_name" value="ETH_B_TXD0"/>
<symbolicName propertyId="p701.symbolic_name" value="ETH_B_REFCLK"/>
<symbolicName propertyId="p702.symbolic_name" value="ETH_B_RXD0"/>
<symbolicName propertyId="p703.symbolic_name" value="ETH_B_RXD1"/>
<symbolicName propertyId="p704.symbolic_name" value="ETH_B_RXER"/>
<symbolicName propertyId="p705.symbolic_name" value="ETH_B_RMII_RXDV"/>
<symbolicName propertyId="p711.symbolic_name" value="I3C_SDA0_PULLUP"/>
<symbolicName propertyId="p800.symbolic_name" value="OSPI_DQ5"/>
<symbolicName propertyId="p801.symbolic_name" value="OSPI_DS"/>
<symbolicName propertyId="p802.symbolic_name" value="OSPI_DQ6"/>
<symbolicName propertyId="p803.symbolic_name" value="OSPI_DQ1"/>
<symbolicName propertyId="p804.symbolic_name" value="OSPI_DQ7"/>
<symbolicName propertyId="p808.symbolic_name" value="OSPI_CK"/>
<symbolicName propertyId="p809.symbolic_name" value="PMOD2_8_RESET"/>
<symbolicName propertyId="p810.symbolic_name" value="PMOD2_9_GPIO"/>
<symbolicName propertyId="p811.symbolic_name" value="PMOD2_10_GPIO"/>
<symbolicName propertyId="p812.symbolic_name" value="ARDUINO_RESET"/>
<symbolicName propertyId="p814.symbolic_name" value="USBFS_P"/>
<symbolicName propertyId="p815.symbolic_name" value="USBFS_N"/>
<symbolicName propertyId="p905.symbolic_name" value="ARDUINO_D4"/>
<symbolicName propertyId="p906.symbolic_name" value="ARDUINO_D2"/>
<symbolicName propertyId="p907.symbolic_name" value="ARDUINO_D3_MIKROBUS_GTIOC13A"/>
<symbolicName propertyId="p908.symbolic_name" value="ARDUINO_D7"/>
<symbolicName propertyId="p909.symbolic_name" value="ARDUINO_D8"/>
<symbolicName propertyId="pa02.symbolic_name" value="PMOD2_3_MISO2_RXD2"/>
<symbolicName propertyId="pa03.symbolic_name" value="PMOD2_2_MOSI2_TXD2"/>
<symbolicName propertyId="pa04.symbolic_name" value="PMOD2_4_SCK2"/>
<symbolicName propertyId="pa05.symbolic_name" value="PMOD2_1_CTS_RTS_SSL2"/>
<symbolicName propertyId="pa06.symbolic_name" value="PMOD2_1_CTS2"/>
<symbolicName propertyId="pa08.symbolic_name" value="PMOD1_8_RESET"/>
<symbolicName propertyId="pa14.symbolic_name" value="JLOB_COMS_TX"/>
<symbolicName propertyId="pa15.symbolic_name" value="JLOB_COMS_RX"/>
<symbolicName propertyId="pb00.symbolic_name" value="I3C_SCL0_PULLUP"/>
<symbolicName propertyId="pb01.symbolic_name" value="USBHS_VBUS"/>
<pincfg active="true" name="RA8M1 EK" selected="true" symbol="g_bsp_pin_cfg">
<configSetting altId="adc0.an000.p004" configurationId="adc0.an000"/>
<configSetting altId="adc0.an001.p005" configurationId="adc0.an001"/>
<configSetting altId="adc0.an004.p007" configurationId="adc0.an004"/>
<configSetting altId="adc0.an007.p014" configurationId="adc0.an007"/>
<configSetting altId="adc0.mode.custom.free" configurationId="adc0.mode"/>
<configSetting altId="adc1.an102.p002" configurationId="adc1.an102"/>
<configSetting altId="adc1.an104.p003" configurationId="adc1.an104"/>
<configSetting altId="adc1.an105.p015" configurationId="adc1.an105"/>
<configSetting altId="adc1.an106.p011" configurationId="adc1.an106"/>
<configSetting altId="adc1.mode.custom.free" configurationId="adc1.mode"/>
<configSetting altId="ether_rmii.pairing.a" configurationId="ether_rmii.pairing"/>
<configSetting altId="iic1.mode.enabled.a" configurationId="iic1.mode"/>
<configSetting altId="iic1.scl1.p512" configurationId="iic1.scl1"/>
<configSetting altId="iic1.sda1.p511" configurationId="iic1.sda1"/>
<configSetting altId="irq12.irq12_dash_ds.p008" configurationId="irq12.irq12_dash_ds"/>
<configSetting altId="irq12.mode.custom.free" configurationId="irq12.mode"/>
<configSetting altId="irq13.irq13_dash_ds.p009" configurationId="irq13.irq13_dash_ds"/>
<configSetting altId="irq13.mode.custom.free" configurationId="irq13.mode"/>
<configSetting altId="irq9.mode.custom.free" configurationId="irq9.mode"/>
<configSetting altId="jtag_fslash_swd.mode.swd.free" configurationId="jtag_fslash_swd.mode"/>
<configSetting altId="jtag_fslash_swd.swclk.p211" configurationId="jtag_fslash_swd.swclk"/>
<configSetting altId="jtag_fslash_swd.swdio.p210" configurationId="jtag_fslash_swd.swdio"/>
<configSetting altId="ospi.mode.custom.free" configurationId="ospi.mode"/>
<configSetting altId="ospi.om_cs1.p104" configurationId="ospi.om_cs1"/>
<configSetting altId="ospi.om_dqs.p801" configurationId="ospi.om_dqs"/>
<configSetting altId="ospi.om_ecsint1.p105" configurationId="ospi.om_ecsint1"/>
<configSetting altId="ospi.om_reset.p106" configurationId="ospi.om_reset"/>
<configSetting altId="ospi.om_sclk.p808" configurationId="ospi.om_sclk"/>
<configSetting altId="ospi.om_sio0.p100" configurationId="ospi.om_sio0"/>
<configSetting altId="ospi.om_sio1.p803" configurationId="ospi.om_sio1"/>
<configSetting altId="ospi.om_sio2.p103" configurationId="ospi.om_sio2"/>
<configSetting altId="ospi.om_sio3.p101" configurationId="ospi.om_sio3"/>
<configSetting altId="ospi.om_sio4.p102" configurationId="ospi.om_sio4"/>
<configSetting altId="ospi.om_sio5.p800" configurationId="ospi.om_sio5"/>
<configSetting altId="ospi.om_sio6.p802" configurationId="ospi.om_sio6"/>
<configSetting altId="ospi.om_sio7.p804" configurationId="ospi.om_sio7"/>
<configSetting altId="p000.input" configurationId="p000"/>
<configSetting altId="p000.gpio_mode.gpio_mode_in" configurationId="p000.gpio_mode"/>
<configSetting altId="p002.adc1.an102" configurationId="p002"/>
<configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
<configSetting altId="p003.adc1.an104" configurationId="p003"/>
<configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
<configSetting altId="p004.adc0.an000" configurationId="p004"/>
<configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
<configSetting altId="p005.adc0.an001" configurationId="p005"/>
<configSetting altId="p005.gpio_mode.gpio_mode_an" configurationId="p005.gpio_mode"/>
<configSetting altId="p007.adc0.an004" configurationId="p007"/>
<configSetting altId="p007.gpio_mode.gpio_mode_an" configurationId="p007.gpio_mode"/>
<configSetting altId="p008.irq12.irq12_dash_ds" configurationId="p008"/>
<configSetting altId="p008.gpio_irq.gpio_irq_enabled" configurationId="p008.gpio_irq"/>
<configSetting altId="p008.gpio_mode.gpio_mode_irq" configurationId="p008.gpio_mode"/>
<configSetting altId="p009.irq13.irq13_dash_ds" configurationId="p009"/>
<configSetting altId="p009.gpio_irq.gpio_irq_enabled" configurationId="p009.gpio_irq"/>
<configSetting altId="p009.gpio_mode.gpio_mode_irq" configurationId="p009.gpio_mode"/>
<configSetting altId="p011.adc1.an106" configurationId="p011"/>
<configSetting altId="p011.gpio_mode.gpio_mode_an" configurationId="p011.gpio_mode"/>
<configSetting altId="p014.adc0.an007" configurationId="p014"/>
<configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
<configSetting altId="p015.adc1.an105" configurationId="p015"/>
<configSetting altId="p015.gpio_mode.gpio_mode_an" configurationId="p015.gpio_mode"/>
<configSetting altId="p100.ospi.om_sio0" configurationId="p100"/>
<configSetting altId="p100.gpio_speed.gpio_speed_hh" configurationId="p100.gpio_drivecapacity"/>
<configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
<configSetting altId="p101.ospi.om_sio3" configurationId="p101"/>
<configSetting altId="p101.gpio_speed.gpio_speed_hh" configurationId="p101.gpio_drivecapacity"/>
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
<configSetting altId="p102.ospi.om_sio4" configurationId="p102"/>
<configSetting altId="p102.gpio_speed.gpio_speed_hh" configurationId="p102.gpio_drivecapacity"/>
<configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
<configSetting altId="p103.ospi.om_sio2" configurationId="p103"/>
<configSetting altId="p103.gpio_speed.gpio_speed_hh" configurationId="p103.gpio_drivecapacity"/>
<configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
<configSetting altId="p104.ospi.om_cs1" configurationId="p104"/>
<configSetting altId="p104.gpio_speed.gpio_speed_h" configurationId="p104.gpio_drivecapacity"/>
<configSetting altId="p104.gpio_mode.gpio_mode_peripheral" configurationId="p104.gpio_mode"/>
<configSetting altId="p105.ospi.om_ecsint1" configurationId="p105"/>
<configSetting altId="p105.gpio_mode.gpio_mode_peripheral" configurationId="p105.gpio_mode"/>
<configSetting altId="p106.ospi.om_reset" configurationId="p106"/>
<configSetting altId="p106.gpio_mode.gpio_mode_peripheral" configurationId="p106.gpio_mode"/>
<configSetting altId="p107.output.low" configurationId="p107"/>
<configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
<configSetting altId="p209.trace.traceswo" configurationId="p209"/>
<configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
<configSetting altId="p210.jtag_fslash_swd.swdio" configurationId="p210"/>
<configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
<configSetting altId="p211.jtag_fslash_swd.swclk" configurationId="p211"/>
<configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
<configSetting altId="p304.trace.tdata3" configurationId="p304"/>
<configSetting altId="p304.gpio_mode.gpio_mode_peripheral" configurationId="p304.gpio_mode"/>
<configSetting altId="p305.trace.tdata2" configurationId="p305"/>
<configSetting altId="p305.gpio_mode.gpio_mode_peripheral" configurationId="p305.gpio_mode"/>
<configSetting altId="p306.trace.tdata1" configurationId="p306"/>
<configSetting altId="p306.gpio_mode.gpio_mode_peripheral" configurationId="p306.gpio_mode"/>
<configSetting altId="p307.trace.tdata0" configurationId="p307"/>
<configSetting altId="p307.gpio_mode.gpio_mode_peripheral" configurationId="p307.gpio_mode"/>
<configSetting altId="p308.trace.tclk" configurationId="p308"/>
<configSetting altId="p308.gpio_mode.gpio_mode_peripheral" configurationId="p308.gpio_mode"/>
<configSetting altId="p407.usbfs.usb_vbus" configurationId="p407"/>
<configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
<configSetting altId="p408.usbhs.usbhs_vbusen" configurationId="p408"/>
<configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/>
<configSetting altId="p409.usbhs.usbhs_ovrcura" configurationId="p409"/>
<configSetting altId="p409.gpio_mode.gpio_mode_peripheral" configurationId="p409.gpio_mode"/>
<configSetting altId="p410.spi1.miso1" configurationId="p410"/>
<configSetting altId="p410.gpio_speed.gpio_speed_h" configurationId="p410.gpio_drivecapacity"/>
<configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/>
<configSetting altId="p411.spi1.mosi1" configurationId="p411"/>
<configSetting altId="p411.gpio_speed.gpio_speed_h" configurationId="p411.gpio_drivecapacity"/>
<configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
<configSetting altId="p412.spi1.rspck1" configurationId="p412"/>
<configSetting altId="p412.gpio_speed.gpio_speed_h" configurationId="p412.gpio_drivecapacity"/>
<configSetting altId="p412.gpio_mode.gpio_mode_peripheral" configurationId="p412.gpio_mode"/>
<configSetting altId="p413.spi1.sslb0" configurationId="p413"/>
<configSetting altId="p413.gpio_speed.gpio_speed_h" configurationId="p413.gpio_drivecapacity"/>
<configSetting altId="p413.gpio_mode.gpio_mode_peripheral" configurationId="p413.gpio_mode"/>
<configSetting altId="p414.output.low" configurationId="p414"/>
<configSetting altId="p414.gpio_mode.gpio_mode_out.low" configurationId="p414.gpio_mode"/>
<configSetting altId="p500.usbfs.usb_vbusen" configurationId="p500"/>
<configSetting altId="p500.gpio_mode.gpio_mode_peripheral" configurationId="p500.gpio_mode"/>
<configSetting altId="p501.usbfs.usb_ovrcura" configurationId="p501"/>
<configSetting altId="p501.gpio_mode.gpio_mode_peripheral" configurationId="p501.gpio_mode"/>
<configSetting altId="p511.iic1.sda1" configurationId="p511"/>
<configSetting altId="p511.gpio_speed.gpio_speed_m" configurationId="p511.gpio_drivecapacity"/>
<configSetting altId="p511.gpio_mode.gpio_mode_peripheral" configurationId="p511.gpio_mode"/>
<configSetting altId="p512.iic1.scl1" configurationId="p512"/>
<configSetting altId="p512.gpio_speed.gpio_speed_m" configurationId="p512.gpio_drivecapacity"/>
<configSetting altId="p512.gpio_mode.gpio_mode_peripheral" configurationId="p512.gpio_mode"/>
<configSetting altId="p600.output.low" configurationId="p600"/>
<configSetting altId="p600.gpio_mode.gpio_mode_out.low" configurationId="p600.gpio_mode"/>
<configSetting altId="p800.ospi.om_sio5" configurationId="p800"/>
<configSetting altId="p800.gpio_speed.gpio_speed_hh" configurationId="p800.gpio_drivecapacity"/>
<configSetting altId="p800.gpio_mode.gpio_mode_peripheral" configurationId="p800.gpio_mode"/>
<configSetting altId="p801.ospi.om_dqs" configurationId="p801"/>
<configSetting altId="p801.gpio_speed.gpio_speed_hh" configurationId="p801.gpio_drivecapacity"/>
<configSetting altId="p801.gpio_mode.gpio_mode_peripheral" configurationId="p801.gpio_mode"/>
<configSetting altId="p802.ospi.om_sio6" configurationId="p802"/>
<configSetting altId="p802.gpio_speed.gpio_speed_hh" configurationId="p802.gpio_drivecapacity"/>
<configSetting altId="p802.gpio_mode.gpio_mode_peripheral" configurationId="p802.gpio_mode"/>
<configSetting altId="p803.ospi.om_sio1" configurationId="p803"/>
<configSetting altId="p803.gpio_speed.gpio_speed_hh" configurationId="p803.gpio_drivecapacity"/>
<configSetting altId="p803.gpio_mode.gpio_mode_peripheral" configurationId="p803.gpio_mode"/>
<configSetting altId="p804.ospi.om_sio7" configurationId="p804"/>
<configSetting altId="p804.gpio_speed.gpio_speed_hh" configurationId="p804.gpio_drivecapacity"/>
<configSetting altId="p804.gpio_mode.gpio_mode_peripheral" configurationId="p804.gpio_mode"/>
<configSetting altId="p808.ospi.om_sclk" configurationId="p808"/>
<configSetting altId="p808.gpio_speed.gpio_speed_hh" configurationId="p808.gpio_drivecapacity"/>
<configSetting altId="p808.gpio_mode.gpio_mode_peripheral" configurationId="p808.gpio_mode"/>
<configSetting altId="p809.output.low" configurationId="p809"/>
<configSetting altId="p809.gpio_mode.gpio_mode_out.low" configurationId="p809.gpio_mode"/>
<configSetting altId="p814.usbfs.usb_dp" configurationId="p814"/>
<configSetting altId="p814.gpio_mode.gpio_mode_peripheral" configurationId="p814.gpio_mode"/>
<configSetting altId="p815.usbfs.usb_dm" configurationId="p815"/>
<configSetting altId="p815.gpio_mode.gpio_mode_peripheral" configurationId="p815.gpio_mode"/>
<configSetting altId="pa02.sci2.rxd2" configurationId="pa02"/>
<configSetting altId="pa02.gpio_speed.gpio_speed_h" configurationId="pa02.gpio_drivecapacity"/>
<configSetting altId="pa02.gpio_mode.gpio_mode_peripheral" configurationId="pa02.gpio_mode"/>
<configSetting altId="pa03.sci2.txd2" configurationId="pa03"/>
<configSetting altId="pa03.gpio_speed.gpio_speed_h" configurationId="pa03.gpio_drivecapacity"/>
<configSetting altId="pa03.gpio_mode.gpio_mode_peripheral" configurationId="pa03.gpio_mode"/>
<configSetting altId="pa04.sci2.sck2" configurationId="pa04"/>
<configSetting altId="pa04.gpio_speed.gpio_speed_h" configurationId="pa04.gpio_drivecapacity"/>
<configSetting altId="pa04.gpio_mode.gpio_mode_peripheral" configurationId="pa04.gpio_mode"/>
<configSetting altId="pa05.sci2.cts_rts2" configurationId="pa05"/>
<configSetting altId="pa05.gpio_speed.gpio_speed_h" configurationId="pa05.gpio_drivecapacity"/>
<configSetting altId="pa05.gpio_mode.gpio_mode_peripheral" configurationId="pa05.gpio_mode"/>
<configSetting altId="pa06.input" configurationId="pa06"/>
<configSetting altId="pa06.gpio_mode.gpio_mode_in" configurationId="pa06.gpio_mode"/>
<configSetting altId="pa14.sci9.txd9" configurationId="pa14"/>
<configSetting altId="pa14.gpio_speed.gpio_speed_h" configurationId="pa14.gpio_drivecapacity"/>
<configSetting altId="pa14.gpio_mode.gpio_mode_peripheral" configurationId="pa14.gpio_mode"/>
<configSetting altId="pa15.sci9.rxd9" configurationId="pa15"/>
<configSetting altId="pa15.gpio_speed.gpio_speed_h" configurationId="pa15.gpio_drivecapacity"/>
<configSetting altId="pa15.gpio_mode.gpio_mode_peripheral" configurationId="pa15.gpio_mode"/>
<configSetting altId="pb01.usbhs.usbhs_vbus" configurationId="pb01"/>
<configSetting altId="pb01.gpio_speed.gpio_speed_h" configurationId="pb01.gpio_drivecapacity"/>
<configSetting altId="pb01.gpio_mode.gpio_mode_peripheral" configurationId="pb01.gpio_mode"/>
<configSetting altId="sci0.mode.custom.free" configurationId="sci0.mode"/>
<configSetting altId="sci1.mode.custom.free" configurationId="sci1.mode"/>
<configSetting altId="sci2.cts_rts2.pa05" configurationId="sci2.cts_rts2"/>
<configSetting altId="sci2.mode.custom.free" configurationId="sci2.mode"/>
<configSetting altId="sci2.rxd2.pa02" configurationId="sci2.rxd2"/>
<configSetting altId="sci2.sck2.pa04" configurationId="sci2.sck2"/>
<configSetting altId="sci2.txd2.pa03" configurationId="sci2.txd2"/>
<configSetting altId="sci4.mode.custom.free" configurationId="sci4.mode"/>
<configSetting altId="sci9.mode.custom.free" configurationId="sci9.mode"/>
<configSetting altId="sci9.rxd9.pa15" configurationId="sci9.rxd9"/>
<configSetting altId="sci9.txd9.pa14" configurationId="sci9.txd9"/>
<configSetting altId="spi1.miso1.p410" configurationId="spi1.miso1"/>
<configSetting altId="spi1.mode.custom.free" configurationId="spi1.mode"/>
<configSetting altId="spi1.mosi1.p411" configurationId="spi1.mosi1"/>
<configSetting altId="spi1.rspck1.p412" configurationId="spi1.rspck1"/>
<configSetting altId="spi1.sslb0.p413" configurationId="spi1.sslb0"/>
<configSetting altId="system.mode.custom.free" configurationId="system.mode"/>
<configSetting altId="trace.mode.custom.free" configurationId="trace.mode"/>
<configSetting altId="trace.tclk.p308" configurationId="trace.tclk"/>
<configSetting altId="trace.tdata0.p307" configurationId="trace.tdata0"/>
<configSetting altId="trace.tdata1.p306" configurationId="trace.tdata1"/>
<configSetting altId="trace.tdata2.p305" configurationId="trace.tdata2"/>
<configSetting altId="trace.tdata3.p304" configurationId="trace.tdata3"/>
<configSetting altId="trace.traceswo.p209" configurationId="trace.traceswo"/>
<configSetting altId="usbfs.mode.custom.free" configurationId="usbfs.mode"/>
<configSetting altId="usbfs.usb_dm.p815" configurationId="usbfs.usb_dm"/>
<configSetting altId="usbfs.usb_dp.p814" configurationId="usbfs.usb_dp"/>
<configSetting altId="usbfs.usb_ovrcura.p501" configurationId="usbfs.usb_ovrcura"/>
<configSetting altId="usbfs.usb_vbus.p407" configurationId="usbfs.usb_vbus"/>
<configSetting altId="usbfs.usb_vbusen.p500" configurationId="usbfs.usb_vbusen"/>
<configSetting altId="usbhs.mode.custom.free" configurationId="usbhs.mode"/>
<configSetting altId="usbhs.usbhs_ovrcura.p409" configurationId="usbhs.usbhs_ovrcura"/>
<configSetting altId="usbhs.usbhs_vbus.pb01" configurationId="usbhs.usbhs_vbus"/>
<configSetting altId="usbhs.usbhs_vbusen.p408" configurationId="usbhs.usbhs_vbusen"/>
</pincfg>
<pincfg active="false" name="R7FA8M1AHECBD.pincfg" selected="false" symbol="">
<configSetting altId="jtag_fslash_swd.mode.jtag.free" configurationId="jtag_fslash_swd.mode"/>
<configSetting altId="jtag_fslash_swd.tck.p211" configurationId="jtag_fslash_swd.tck"/>
<configSetting altId="jtag_fslash_swd.tdi.p208" configurationId="jtag_fslash_swd.tdi"/>
<configSetting altId="jtag_fslash_swd.tdo.p209" configurationId="jtag_fslash_swd.tdo"/>
<configSetting altId="jtag_fslash_swd.tms.p210" configurationId="jtag_fslash_swd.tms"/>
<configSetting altId="p208.jtag_fslash_swd.tdi" configurationId="p208"/>
<configSetting altId="p208.gpio_mode.gpio_mode_peripheral" configurationId="p208.gpio_mode"/>
<configSetting altId="p209.jtag_fslash_swd.tdo" configurationId="p209"/>
<configSetting altId="p209.gpio_mode.gpio_mode_peripheral" configurationId="p209.gpio_mode"/>
<configSetting altId="p210.jtag_fslash_swd.tms" configurationId="p210"/>
<configSetting altId="p210.gpio_mode.gpio_mode_peripheral" configurationId="p210.gpio_mode"/>
<configSetting altId="p211.jtag_fslash_swd.tck" configurationId="p211"/>
<configSetting altId="p211.gpio_mode.gpio_mode_peripheral" configurationId="p211.gpio_mode"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>